Since the introduction of the IC devices, workers have been trying to increase the IC density, and reduce the cost of manufacturing chips. The first approach means to put more components/functionality onto a chip. The second approach is to build more chips on a larger substrate. The substrate Si wafer processing facility has grown from 2.5 IN diameter to 12 IN. One wafer may hold 10 k full dices to reduce the unit costs. A common need to serve both purposes well is to reduce the physical dimensions of each circuit's elements.
Various attempts were tried in the past to improve IC functionality, performance, and cost figures. The early IC implementations were done via the bipolar junction transistors, where layers of various diffusion regions were stacked vertically, and isolated transistor pockets contain the three vital terminal switching terminals, among other R and C circuit elements.
FIG. 1a-1d shows the schematics of the physical layout of the basic transistor in BJT and FET or metal on silicon (MOS) eras. One can see that the FET is always more compact (about 2.5:1 or more) than the BJT. The drawing showed the transistors with a minimum number of contacts. If one measures the dimension with the minimum feature ‘F’ size, the isolated BJT takes 20F2 area versus the MOST 10F2. Other circuit components, which have more enclosure contacts in layout implementations, may have more pronounced area impacts.
For the last decade of IC implementations, it was V-I scaling that has been needed in order to house more components on a chip. The device complexity has grown to over billions of circuit elements with complementary MOS (CMOS) constructs. Still more complications were added to the devices; the Flash transistors as memory blocks, almost doubled in process and mask steps and added complicated circuit manipulations.